This invention relates to large scale integration (LSI) and very large scale integration (VLSI) circuit chips that use complementary metal oxide semiconductor (CMOS) technology. More particularly, the invention relates to a CMOS circuit that can selectively function as either a synchronous latch, an asynchronous latch, or a stage of a shift register, using the same clock signals as used by the synchronous latch circuit.
A synchronous latch circuit requires a clock signal to cause it to operate. When the clocking signal occurs, the logic level, or data, that was on an input of the latch immediately prior to the clock signal is stored in the latch. An asynchronous latch circuit on the other hand, does not use a clock signal. It typically has three inputs; a signal input, a reset input, and a feedback input (which feedback input is connected to the output). When an asynchronous latch is reset, it will set (the output changes state) whenever the signal input changes to the correct logic level. Moreover, it will remain set, because of the feedback signal, regardless of subsequent changes in the signal input. The asynchronous latch circuit is reset by momentarily changing the reset signal.
A central processing unit (CPU) of a modern large computer system basically includes synchronous latch circuits, combinatorial logic circuits, i.e., logic circuits that do not store data, and a clocking system. The inputs to the latch circuits come from the outputs of combinatorial logic circuits while the outputs of the latches go to the inputs of other combinatorial logic circuits. At the end of a clock cycle, which is also the beginning of the next clock cycle, the data on the outputs of the combinatorial logic circuits is stored in the synchronous latch circuits to which they are connected. This data appears on the outputs of the synchronous latch circuits and is applied to the inputs of other combinatorial logic circuits, which logic circuits then perform the desired logic function on the data. At the end of the clock cycle, the outputs of all the combinatorial logic circuits are again stored in synchronous latch circuits. This process is repeated over and over as the computer system operates; that is, data is processed by the combinatorial logic circuits, stored in synchronous latch circuits, and each set of combinatorial logic circuits receives a new set of data for processing from the data just stored in the synchronous latch circuits.
As described above, the operation of a large computer is synchronous. However, the peripheral devices connected to the computer, such as magnetic disk storage systems, terminals, communication devices, etc., do not use the clocking system of the CPU to operate, and hence operate asynchronously with respect to the CPU. Also, signals from a peripheral device can occur at any time and can be shorter in duration than the clock cycle of the CPU. If such a signal were applied to the input of a synchronous latch in the CPU, it might be gone when the clock signal occurs and therefore not be latched. Hence, signals from peripheral devices are typically applied to the input of an asynchronous latch. Once latched in the asynchronous latch, the signal from the peripheral equipment can be processed in a synchronous manner by the CPU.
While the use of an asynchronous latch circuit in a synchronous computer provides the advantage of "capturing" asynchronous signals, it has the disadvantage, as explained below, of not being testable in the same manner as the synchronous latch circuits. One circuit common in large computer systems is a "scannable" synchronous latch. Such a latch circuit can be converted to a stage of a shift register by use of appropriate clock and control signals. The contents of the synchronous latch circuit can be "scanned" by using the resulting shift register stage to shift out the contents for examination. The shift register stage, and therefore the synchronous latch circuit, can also be loaded with the desired contents by shifting new data thereinto. (Hereafter, a "latch circuit" may simply be referred to as a "latch".)
When all of the synchronous latches of a CPU are of the scannable type as described above, selected sets can be interconnected to form shift registers. Appropriate timing signals can then be used to stop the operation of the CPU at any time, convert the synchronous latches into stages of a shift register, and scan the contents of the latches, e.g., shift the contents of the resulting shift register to an operator's console for examination. Any, or all, of the resulting shift registers can be thus examined. Also, while the operation of the CPU is stopped, a known set of data can be shifted into any or all of the sets of latches via the shift registers. With this known set of data loaded into the CPU, the CPU can then be allowed to function for some known number of cycles and then stopped again. The appropriate latches can then be scanned to see if they contain the correct results.
As thus described, the scannable synchronous latch provides a powerful feature for testing a large computer. Using the techniques highlighted above, all the synchronous latches and their associated combinatorial logic circuits can be fully tested.
Disadvantageously, asynchronous latch circuits of the prior art cannot be converted to a shift register stage, and therefore cannot be tested in the manner described above. This is not to say that such asynchronous latch circuits cannot be tested. As an individual packaged chip, it is usually possible to fully test any asynchronous latch using a suitable chip tester. This is possible since the asynchronous latch is used to receive asynchronous signals from external sources through the input pins of the chip package. Since chip testers usually have the ability to control all the inputs to the chip, as well as to monitor all the outputs from the chip, the asynchronous latch can be set or reset, as desired, by the chip tester as the chip is individually tested.
However, once the chip becomes part of a larger system, such as a computer system, the inputs to the asynchronous latches are controlled by the overall system within which the chip is used (e.g., by the peripheral equipment connected to the computer system). Thus, inputs of the asynchronous latch can no longer be fully controlled, and the asynchronous latch can not be fully tested. Unfortunately, this means that other circuits on the chip cannot be tested as well. This is because the output of an asynchronous latch is typically applied to the input of one or more combinatorial logic circuits. Since these inputs can not be controlled, the combinatorial logic circuits can not be fully tested.
This particular problem of lack of testability in the system environment is particularly acute when the system includes LSI and VLSI circuit chips where a very large number of circuits are included on the same chip. Particularly in the field of CMOS technology, where circuit densities on a chip and overall system compactness have the potential for dramatic increases over what has heretofore been achievable, it is extremely critical that a suitable chip be developed that can be tested both individually and within the system.
It can thus be seen that a need exists in the art, especially in the CMOS technology art, for a scannable asynchronous latch circuit. So as not to unduly complicate the operation of such a scannable asynchronous latch, it would be advantageous for such a circuit to be controlled during system test by the same clock signals that control the synchronous latches on the same chip.